Google's TPU push could redefine AI hardware throughput by 2028

Google is planning a massive ramp in its in-house AI chip production, aiming to deploy between 12 million and 15 million ninth-generation TPUs by 2028. According to a research note from Fubon, that volume would put a single cloud provider on par with Nvidia's projected data center GPU shipments of around 12.4 million units in the same year. The TPU v9 will use four compute dies, a multi-die design that more than doubles capacity requirements compared with 2027 levels. This move signals that AI hardware competition is increasingly about deployment volume and supply chain control, not just chip performance.

What happened

Fubon Research estimates that Nvidia supplied 8.2 million data center GPUs in 2026 and could reach 12.4 million by 2028. Google's target of 12-15 million TPUs would place it in the same range, marking a notable shift where a cloud provider produces accelerator volume comparable to the leading merchant chip supplier. The TPU v9 generation will use four compute dies, consistent with the industry's move to multi-die designs. Manufacturing at that scale introduces serious constraints. Fubon's analysts suggest that TSMC alone may not be able to meet Google's demand, pointing to a potential role for Intel Foundry. Recent reports indicate that Intel has already secured orders to produce millions of TPUs after Google tested its advanced packaging capabilities. Packaging technologies differ across manufacturers: designs built around Intel's EMIB or EMIB-T are not directly compatible with TSMC's CoWoS-L, adding complexity to the supply chain.

Why AI builders should care

If Google reaches its 2028 target, it would likely become the largest single user of AI accelerators. That does not mean it will stop buying from Nvidia, but it would give the company far more control over its compute stack and supply. For AI builders, this could reshape cloud economics and deployment pipelines. A diversified supply chain is already taking shape: Google is working with Broadcom on a training chip codenamed Sunfish and with MediaTek on an inference chip called Zebrafish, aiming for 20-30% lower inference cost. Marvell is also in talks to add a memory processing unit and an additional inference TPU. This multi-partner strategy reduces dependency on any single foundry or packaging technology, which matters for availability and pricing of AI hardware.

Practical implications

The race is moving beyond chip-level benchmarks to total accelerator deployment volume and supply chain resilience. For teams planning AI infrastructure, Google's roadmap suggests that custom silicon from cloud providers could become a more predictable and cost-effective option for large-scale training and inference workloads. The involvement of Intel Foundry and the evaluation of EMIB/EMIB-T packaging alongside TSMC's CoWoS-L indicate that advanced packaging capacity is a real bottleneck. Builders should watch how these manufacturing decisions affect lead times and pricing for Google Cloud TPU instances. If Google achieves its 2028 volume, it could shift vendor leverage and negotiation dynamics for AI infrastructure procurement.

Caveats

These production targets and packaging details come from analyst notes and industry reporting, not official Google confirmations. Performance comparisons between TPU v9 and Nvidia's next-generation systems, including Rubin and Rubin Ultra, are not yet available. The exact mix of foundries, packaging technologies, and final chip specifications could change as designs mature. Treat the 12-15 million figure as a directional signal rather than a firm commitment.