PicoJool raises $27.5M to scale VCSEL optical interconnects for AI clusters
Published by AINave Editorial • Reviewed by Ramit
PicoJool, a startup backed by former Intel CEO Pat Gelsinger, raised $27.5 million in a Series A round to scale its VCSEL optical interconnect technology for AI clusters. The round, led by Socratic Partners with participation from Hudson River Trading, brings total funding to $39.5 million. The company claims its high-speed VCSEL modules can unclog the interconnect bottleneck that limits scaling of large GPU clusters SiliconANGLE.
The bandwidth wall is real for AI cluster operators
As training and inference deployments push into clusters of hundreds or thousands of accelerators, interconnecting them becomes a performance and cost problem. Copper wiring cannot keep up with the bandwidth demands of distributed training, and it consumes significant power driving signals across racks. PicoJool's approach uses Vertical Cavity Surface Emitting Lasers (VCSELs), a type of semiconductor laser diode that transmits data as light over optical cables. The startup offers 100G and 200G VCSEL lines plus MicroVCSEL configurations at 50G NRZ and 64G NRZ/PAM4, promising much faster and more energy-efficient data movement between chips SiliconANGLE.
Pat Gelsinger, whose venture firm Playground Global led the seed round, framed the problem succinctly: "The network is the AI, and connectivity is becoming one of the defining constraints on performance." For builders operating clusters at scale, every microsecond and watt spent on data movement directly impacts training throughput and inference latency.
What changes practically: from chip to module
PicoJool's roadmap goes beyond individual VCSEL chips. The company plans to integrate its technology into Active Optical Cables (AOC) and Near-Packaged Optics (NPO) modules, which data-center operators can deploy as drop-in replacements for copper interconnects. The MicroVCSEL architecture uses a massively parallel design that aggregates bandwidth while reducing energy per bit, with a stated pathway to 3.2 terabits per second of aggregate bandwidth SiliconANGLE.
CEO Al Yuen emphasized execution over R&D: "Reaching 200G per lane proved that the performance is there. Our focus is now execution." The new funding will expand teams in the US and Taiwan, qualify products with customers, and scale manufacturing. PicoJool is working with WIN Semiconductors and other foundries to prepare the 200G VCSEL for mass production SiliconANGLE.
Caveats and what remains unconfirmed
The announcement is a funding milestone, not a product shipment. PicoJool's bandwidth claims are vendor-reported, and no independent benchmarks or third-party validation are available yet. The 3.2 Tbps figure is a roadmap target, not a current shipping specification. Mass-production readiness depends on WIN Semiconductors and other partners meeting unspecified timelines. Builders evaluating interconnect upgrades will want to see qualified modules shipping before making purchasing decisions. The company itself states it needs to "qualify products with customers" as a next step.
For now, PicoJool's raise signals that the optical interconnect space is attracting serious capital and talent. If execution follows, operators of large GPU clusters may have a new option for breaking through the bandwidth bottleneck that constrains today's AI workloads.
