Probabilistic computing with p-bits: 1 million p-bits across 18 FPGAs

Researchers have built the largest probabilistic computer to date, wiring 1 million probabilistic bits (p-bits) across 18 FPGAs to create a system capable of over a trillion flips per second. This milestone in probabilistic computing with p-bits demonstrates a scalable, multi-chip architecture that could eventually tackle stochastic optimization problems beyond the reach of traditional computers, while avoiding some of the hardware challenges of quantum computing.

What happened

A team led by Kerem Çamsarı at UC Santa Barbara, in collaboration with Navid Anjum Aadit and Xiuqi Zhang, networked 18 field-programmable gate arrays (FPGAs) to create a probabilistic computer with 1 million p-bits. The machine is programmable and general-purpose, unlike hardwired Ising machines or QUBO devices. It achieves over a trillion p-bit flips per second and communicates data between chips without global lockstep synchronization, using a predictable design rule for inter-chip data exchange that preserves speed and accuracy below a defined threshold.

Prior work included a 2019 Nature study with eight p-bits and a 2023 effort with 7,200 p-bits on single chips. The new approach networks multiple chips for larger scales, suggesting a path toward arbitrarily large probabilistic computers. The study was detailed on ArXiv on 24 June by Çamsarı and colleagues.

Why AI builders should care

This work shows a programmable, general-purpose approach to probabilistic computing that can scale across multiple chips. For AI builders working on optimization, sampling, or probabilistic inference, this could lead to specialized hardware that is more energy-efficient and faster for certain stochastic tasks. The design rule for inter-chip communication is a key insight that could influence future hardware architectures for probabilistic computing.

In the longer term, probabilistic computing hardware could leverage existing technologies such as magnetic tunnel junctions and CMOS+MRAM to improve energy efficiency and scalability for probabilistic problem solving. This is relevant for AI workloads that involve stochastic optimization, such as reinforcement learning, Bayesian inference, or combinatorial optimization.

Practical implications

The machine's trillion flips per second suggests potential for fast stochastic sampling and optimization tasks. The simple data-exchange rule means larger networks are feasible without complex synchronization. The researchers note that the findings apply to probabilistic computers built from essentially any hardware, opening the door to specialized chips for probabilistic computing in the future.

For builders evaluating hardware for stochastic problems, this work provides a blueprint for scaling probabilistic computers by networking many chips, similar to how standard computers scale today.

Caveats

The study notes tradeoffs between speed and accuracy when operating below a certain inter-chip data-exchange threshold. Scaling to multi-chip systems presents challenges not present in single-chip implementations, including maintaining correlated fluctuations across wires and avoiding premature synchronization.

Public experimental details are limited in summaries; some claims rely on an ArXiv preprint and IEEE Spectrum coverage rather than full peer-reviewed data. The work is still research, not a product, and practical deployment for AI workloads remains speculative.

FAQs

P-bits are probabilistic bits that flip between 0 and 1 with a tunable probability. When many such noisy bits operate together in a correlated fashion, they can solve stochastic problems that operate on probabilities rather than concrete numbers. P-bits bridge conventional bits and qubits by enabling programmable probabilistic computation rather than single-problem hardwired logic. The discussed work uses p-bits across multiple FPGAs to form a scalable probabilistic computer.