Meta reuses DDR4 memory in DDR5 AI servers with custom CXL ASIC

Meta has disclosed a practical approach to reusing old DDR4 memory in new DDR5-only AI servers, enabled by a custom CXL ASIC called Vistara. The design treats DDR4 as a separate NUMA node, keeping hot data in fast DDR5 while cold pages reside in slower DDR4. Meta claims this reduces AI inference server count by up to 25% and cuts job-restart and fragmentation overhead by about 33%.

What happened

Meta presented its work at ISCA 2026, detailing how its new "MemServers" use AMD Epyc Turin CPUs (158 cores, 316 threads) that officially support only DDR5. To get around that limitation, Meta built a custom CXL 2.0 ASIC named Vistara that bridges legacy DDR4 DIMMs to the host processor over a PCIe Gen5 x16 interface. Each MemServer packs 1 TB of total memory: 768 GB of DDR5-6400 local RAM and 256 GB of DDR4-2400 CXL-attached RAM.

The Vistara software stack treats the DDR4 memory as a "distinct, CPU-less NUMA node," separate from the local DDR5 DRAM nodes. This lets the system keep frequently accessed data in faster DDR5 while relegating cold pages to the slower DDR4 pool. Meta also modified the Linux CXL driver to get the older DIMMs working on platforms that don't officially support them, and noted that all kernel CXL driver code used for Vistara is either already upstream or on track to be added soon.

Meta is not alone in this direction. South Korean fabless semiconductor firm Panmnesia also presented its own CXL controller and a PCIe 6.4/CXL 3.2 Fusion Switch at ISCA 2026, giving hyperscalers another way to cut hardware spending through mixed-memory architectures.

Why AI builders should care

For teams building and deploying AI inference at scale, memory cost is a growing pain point. DDR5 prices remain high, and AI workloads demand large memory pools for model weights, KV caches, and intermediate data. Meta's approach shows that CXL memory expanders can make older, cheaper DDR4 usable alongside modern DDR5 without crippling latency penalties.

This matters because it opens a path to lower total cost of ownership for inference servers. If you can reuse decommissioned DDR4 DIMMs or buy cheap DDR4 on the secondary market, you can expand memory capacity at a fraction of the cost of all-DDR5 builds. The key insight is that not all memory needs the same speed: cold pages (infrequently accessed data) can live on slower memory without hurting inference throughput.

Practical implications

For AI builders, the immediate takeaway is that CXL-based memory tiering is becoming production-ready. Meta's Vistara ASIC is a first-generation custom chip, but the underlying CXL 2.0 standard is open and supported by major CPU vendors. As CXL memory expanders become more common, we may see commercial off-the-shelf solutions that let any hyperscaler or large-scale AI operator mix memory generations.

The modified Linux CXL driver being upstreamed means the software stack is becoming standard, reducing the custom engineering burden. For teams running large inference fleets, this could translate to:

• Fewer servers needed for the same inference throughput (Meta claims up to 25% reduction).
• Lower job-restart and fragmentation overhead (33% reduction), which improves utilization.
• Ability to extend the life of existing DDR4 inventory, reducing e-waste and procurement costs.

However, this approach is not a drop-in solution for most builders. It requires custom ASICs (or commercial CXL memory expanders), a modified kernel driver, and careful NUMA-aware workload placement. Smaller teams without hardware engineering resources will likely need to wait for standardized CXL memory expander products.

Caveats

• Meta's claims (25% fewer servers, 33% overhead reduction) are based on its own internal testing and have not been independently verified. Real-world savings will depend on workload memory access patterns.
• The Vistara ASIC is custom silicon, not available for purchase. Panmnesia's CXL products are still in sampling and development stages.
• Mixing DDR4 (2400 MT/s) with DDR5 (6400 MT/s) creates a significant speed gap. The approach works only if the workload has enough cold data to offload without impacting latency-sensitive inference.
• The modified Linux CXL driver is not yet fully upstream, though Meta says it is on track. Production deployments will need to track kernel updates carefully.